1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, and in particular, to a negative-voltage row-decoder circuit in a flash EEPROM (Electrically Erasable/Programmable Read Only Memory).
2. Description of the Related Art
When writing or erasing data into or from a flash EEPROM with memory cells each having a floating gate, application of a negative voltage to a gate of a memory transistor is a very important technique in attaining low voltage and high reliability of the device. If the writing or erasing of data is done in a small unit of capacity, a row decoder circuit to supply only a selected word line with a negative or high voltage is required.
Now, description is made as to memory cells in such a flash EEPROM. Table 1 shows exemplary conditions of bias voltage applied to respective terminals of a memory cell when erase and write operations are performed by using Fowler-Nordheim tunnel current. FIGS. 1A and 1B are schematic sectional views of the memory cell in the respective operations. In read-out operation, a control gate 31 is supplied with 5.0 V, a drain 33 with 1.0 V and a source 32 is grounded, so that a current flowing through the memory cell is sensed. In erase operation, a voltage of 15 V (Vg) is applied to the control gate 31, and the drain and the source are grounded, as shown in FIG. 1A, where electrons are injected from the substrate into the control gate 31. In write operation, a voltage of -9.0 V (Vg) is applied to the control gate 31, 5.0 V (Vd) to the drain 33 and the source 32 is grounded, as shown in FIG. 1B, where electrons escape from the control gate 31 and enter the drain 33.
TABLE 1 ______________________________________ Vcg Vd Vs VH VL ______________________________________ Read- 5.0 V/0.0 V 1.0 V/0.0 V 0.0 V 5.0 V 0.0 V Out Erase 15.0 V/0.0 V 0.0 V/0.0 V 0.0 V 15.0 V 0.0 V Write -9.0 V/0.0 V 6.0 V/0.0 V 0.0 V 3.0 V -9.0 V (Select/ (Select/ Non-Select) Non-Select) ______________________________________
FIG. 2 is a block diagram of a conventional row decoder circuit which satisfies the conditions of bias voltage applied to the control gate of a memory cell. The row decoder circuit is provided with a positive voltage decoder 41 for each word line so that erase and read-out operations will be performed for each word line, and a negative voltage decoder 42 for supplying a negative voltage to only a selected word line during write operation. The row decoder circuit also includes a P-channel transistor 43 for separating the positive voltage decoder 41 from the negative voltage decoder 42.
Since the row decoder circuit of FIG. 2 needs the negative voltage decoder 42 for supplying a negative-voltage to each word line when writing data and the P-channel transistor 43 for blocking the negative voltage, the area of the row decoder circuit becomes very large to prevent high integration of the circuit and hence to increase the chip size.
FIG. 3 is a circuit diagram of a negative voltage row decoder disclosed in Japanese Patent Laid-Open Appliction No. Hei 06-215591, which shows another conventional example. In FIG. 3, an input address signal is passed through an inverter 25b and handled as a complementary signal. And, using two transfer gates to be controlled by a write signal 62, the logic level of the address is inverted between the write mode and the other modes (erase and read). The address signal is level-converted by an inverter section 46 consisting of two-stage level shifters 21b, 22b and two inverters, and is output as a selected address signal RAI51.
The level shifters 21b, 22b consist of two P-channel transistors and two N-channel transistors, respectively. In the level shifter 22b, each source of P-channel transistors Q35, Q36 is connected to a potential VH, and each source of N-channel transistors Q37, Q38 is grounded. In the level shifter 21b, each source of P-channel transistors Q31, Q32 is connected to the potential VH, and each source of N-channel transistors Q33, Q34 is connected to a potential VL. The two inverters are supplied with the potentials VH and VL respectively. The potential VH is a high potential (e.g., 15 V) during erase operation, which is supplied from an internal power generating circuit, and a power source potential VCC in the other modes. The potential VL is a negative potential (e.g., -9 V) during write operation and a ground potential in the other modes. Thus, the address signal is converted by the level shifter 22b into a VH-GND potential type signal, and in turn, by the level shifter 21binto a VH-VL potential type signal. The row decoder circuit having such a structure permits application of negative voltage to only a certain word line during write operation, but needs individual address logic inverting circuits for inverting the logic level of the address between the write mode and the other modes. Since it also outputs the VCC level to non-selected word lines during write operation, it is difficult to maintain the operating conditions as shown in Table 1.
Such conventional nonvolatile semiconductor memories need either positive and negative row decoders for applying a negative voltage to a word line, or an input address logic inverting circuit for inverting the input address signal between write mode and the other modes. Therefore, a problem arises with the conventional nonvolatile semiconductor memories that the number of transistors constituting a row decoder and hence the chip size increases. Further, since the VCC level is output to the non-selected word lines during write operation, the non-selected word lines may be disturbed.